Board Technology: ASIC Prototyping , Embedded Design, General Purpose
Designing for high performance serial transceiver applications using series 10 Intel® FPGAs / Arria® 10 GX 1150 KLEs.Hardware, software design tools, IP, and pre-verified reference designsLoopback boards, cables, and extension IOs board are available in the kit contentPCIe with 8 lanes at 8 Gb/s link rate (Gen3)Advanced memory interface with DDR4 SODIMM Memory up to 16 GB, support ECC and Non ECCEnabling serial connectivity with QSFP+ with 4 XCVR links: 12.5 Gb/s per link*Develop networking applications with RJ45 copper connector 10/100/1000 Base-T Ethernet (Through RGMII PHYâ€‹)Implement Video display applications with Display output port Rev 1.2 (up to 5.4Gbit/s)Expand I/O connector with 2 connectors in order to improve a front end of 32 high speed link.On board programmable PLL oscillator (Si5341), highly flexible and configurable clock generator/buffer.The board respect the VITA57.1 standard, you can plug FPGA Mezzanine Card (FMC) on the front endThe FMC interface provides High Pin Count (HPC) fully populated, compliant +1.8V only (+vadj)•160 LVCMOS (1.8V) usable as 80 LVDS (1.8V, 2.5V)•4 dedicated LDVS clocks that respect the VITA57.1 pinout assignment usable as LVDS signals or 8 LVCMOS•10 XCVR (up to: 12.5 Gb/s)** Production Device with transceiver speed grade 4 can reach 12.5 Gb/s chip to chip links, The VITA 57.1 standard allows interfaces up to 10 Gb/s
Available on request through REFLEX CES support web site.
Y. On request
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Test Plan Summary
When using the ARRIA 10 FPGA FMC IDK for the first time the user can launch the innovative Graphical User Interface and discover the Kit interfaces, applications and performances. The USB key also contains all the files required to enable test interfaces or help the user to start his own design. We provide the user an ATTILA Top_Arria10 folder which contains a blank Quartus II project intended for building a custom design "from scratch".
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