The LP-Serial Endpoint Core implements all of the functions are defined in the RapidIO Physical Layer LP-Serial Specification Rev. 2.2. Figure 1 illustrates the overall architecture of the core.The core integrates an IO Logical Layer Initiator that maps AXI4 transactions into RapidIO IO Logical request packets. The user interface consists of a 64-bit or 128-bit AXI4 slave interface.The core also integrates an IO Logical Layer Target that maps RapidIO IO Logical request packets into AXI4 transactions on the user interface. This user interface consists of a 64-bit or 128-bit AXI4 master interface.In addition to the RapidIO Physical layer functions, the core also includes Management Module that supports access to Physical, Transport, and Logical Layer CSRs either through maintenance transactions, or through the AXI4-lite Local Management Interface (LMI).
Device Utilization and Performance
Varies widely with options chosen. Contact Praesum for utilization for your configuration.
Evaluation design pre-integrated with Linux demo application for Cyclone® V SOC on Arrow SocKit board.
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Modelsim / Questa
Y. Altera Board Name Arrow SocKit
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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