RapidIO 2.x LP-Serial Physical Layer Endpoint Core
Block Diagram
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Overview
The LP-Serial Endpoint Core implements all of the functions are defined in the RapidIO Physical Layer LP-Serial Specification Rev. 2.2. Figure 1 illustrates the overall architecture of the core.The core integrates an IO Logical Layer Initiator that maps AXI4 transactions into RapidIO IO Logical request packets. The user interface consists of a 64-bit or 128-bit AXI4 slave interface.The core also integrates an IO Logical Layer Target that maps RapidIO IO Logical request packets into AXI4 transactions on the user interface. This user interface consists of a 64-bit or 128-bit AXI4 master interface.In addition to the RapidIO Physical layer functions, the core also includes Management Module that supports access to Physical, Transport, and Logical Layer CSRs either through maintenance transactions, or through the AXI4-lite Local Management Interface (LMI).
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2004 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | Y |
| Driver OS support | Linux |
| Implementation | |
| User Interface | AXI |
| IP-XACT Metadata included | Y |
| Verification | |
| Simulators supported | Modelsim / Questa |
| Hardware validated | Y. Altera Board Name Arrow SocKit |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | Y |
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