DSN Member Profile: Praesum Communications

Praesum Communications


With over 17 years of experience in high performance computing and communications, Praesum is uniquely positioned to help customers develop next generation systems for demanding applications. We offer complete system level design services including software, board and SOC IP development. FPGA IP is developed using an ASIC class design and verification flow, ensure deterministic project completion. In addition to these services Praesum offers RapidIO endpoint and switching IP as well as the ability to create high performance switches for custom applications. This IP is pipelined for consistent timing closure on FPGAs, but ASIC proven.

Available Design Services

Design Services Device Family Country/Region Supported
Design Verification: Power Analysis, Timing Analysis, Schematic Review, Layout Analysis
Embedded Design: ARM* Drivers, ARM* Applications, ARM* Middleware
Altera Training
Hardware Design: FPGA + CPU, Specification Development, System-Level Board design, FPGA, High Speed Transceiver, Timing Closure
IP Integration
Stratix® V, Intel® Arria® 10 SoC, Cyclone® V, Cyclone® V SoC, Intel® Arria® 10 Americas: United States

Additional Services and Features

‧    OpenCL Development / Design Optimization

‧    Protocol Bridging

‧    Soc Development

‧    RapidIO Endpoint and Switching IP

Contact Information

3558 Round Barn Blvd
Suite 200
Santa Rosa, California United States
Tel:(707) 338-0946