iPORT NTx-U3 Intellectual Property

Block Diagram

Solution Type: IP Core

End Market: Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore

Technology: DSP: Video and Image Processing

Cyclone Series: Cyclone® V


Pleora's iPORT NTx-U3 Intellectual Property (IP) is a package of tools, reference designs, and expert design services that allows system and camera manufacturers to fully integrate USB3 Vision connectivity in imaging devices. The iPORT NTx-U3 IP Core Package allows manufacturers to reduce overall system costs by creating Intel® Cyclone® V FPGA loads which fully integrate their logic with Pleora's iPORT NTx-U3 IP core. This FPGA load can be paired with custom hardware developed with the iPORT NTx-U3 Hardware Reference Design.Pleora's IP core platform increases flexibility and reduces costs for manufacturers by providing a straightforward design path to integrate their logic with the iPORT NTx-U3 IP Core in a custom FPGA load. Designers can utilize a single FPGA to perform pixel correction, color space conversion, and other specialized analysis tasks as well as incorporating USB3 Vision functionality.


  • Create a custom FPGA load integrating your logic with Pleora's iPORT NTx-U3 IP core
  • Intgerate pixel correction, color space conversion, and specialized tasks with NTx-U3 IP core
  • Compatible with the USB3 Vision and GenICam standards

Device Utilization and Performance

Intel Cyclone V, pixel bus to USB3 load provided by Pleora, user defined to USB3 Vision load created by customer based on the Pleora IP Core Package, Backup and main loads provided by Pleora, FPGA load licensable with iPORT Authorizer

Getting Started

The iPORT NTx-U3 Hardware Reference Design allows manufacturers to develop customized hardware based on the design of Pleora's iPORT NTx-U3 Embedded Video Interface hardware. The customized hardware can be paired with Pleora's off-the-shelf FPGA load, or with a customized FPGA load created with the iPORT NTx-U3 IP Core Package.

IP Quality Metrics

Year IP was first released2013
Latest version of Quartus supported14.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerN

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Testbench languageVHDL
Software drivers providedY
Driver OS supporteBUS SDK
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedModelSim
Hardware validated N. Altera Board Name Enclustra Mars AX3
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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