XpressSWITCH

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Military, Test & Measurement, Wireless

Evaluation Method: Source Code

Technology: Interface Protocols: PCI Express

Arria Series: Intel® Arria® 10

Overview

XpressSWITCH is a customizable, multiport embedded Switch for PCIe designed for ASIC and FPGA implementations enabling the connection of one upstream port and multiple downstream ports and fully configurable. XpressSWITCH is the first embedded switch IP available on the market and enables designers to use fewer PCIe PHYs, saving latency, power consumption and bill-of-material.

Features

  • 1 upstream port, up to 31 downstream ports Up to x16 link width per port Link rate of up to 16 Gbps
  • (PIPE) 4.x compliant , Single Virtual Channel (VC) implementation, AER, ECRC, ARI, Hotplug
  • Independent configuration of link width, link speed, equalization settings, and PIPE interface width per-PCIe port
  • Peer-to-peer, Broadcast and Multicast, Round-Robin arbitration,
  • No Packet buffering, Data Protection, Integrated Clock Domain Crossing

Device Utilization and Performance

The XpressSWITCH IP transparently manages upstream-downstream data flow as well as peer-to-peer transfers between downstream ports, delivering the flexibility, scalability and configurability required for connecting multiple devices, including NVMe SSDs.

Getting Started

Available

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported17.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportN
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportLinux, WIndows
Implementation
User InterfaceOther: Other: Tx/Rx
IP-XACT Metadata includedN
Verification
Simulators supportedPLDA
Hardware validated Y. Altera Board Name ARRIA 10 DevKit
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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