Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: PCI Express

Arria Series: Intel® Arria® 10, Arria® V

Stratix Series: Stratix® V


XpressRICH3 is a highly configurable PCIe interface Soft IP designed for ASIC and FPGA implementations. With advanced features such as SR-IOV and data-path protection, and numerous tape-outs on leading edge process technologies, XpressRICH3 is the industry’s PCIe IP of choice for enterprise-class applications requiring the highest performance, reliability, and flexibility.


  • Supports up to x8 at PCIe 1.0/2.0/3.0 speeds ( Endpoint, Root Port, Switch, Dual Mode)
  • Virtualization ready with SRIOV and ATS/ARI
  • Data Protection (ECC, ECRC) End-End TLP prefixes
  • L1 PM substate with CLKREQ, ASPM and legacy power management

Device Utilization and Performance

Contact us to know the device utilization and Performance for your configuration

Getting Started


IP Quality Metrics

Year IP was first released2012
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportN
Source language
Testbench languageVerilog
Software drivers providedY
Driver OS supportLinux, Windows
User InterfaceOther: Tx/Rx
IP-XACT Metadata includedN
Simulators supportedPLDA
Hardware validated Y. Altera Board Name XpressGX5LP
Industry standard compliance testing performed
If yes, which test(s)?PCI-SIG
If yes, on which Altera device(s)?STRATIX V
If Yes, date performed
IP has undergone interoperability testing
Interoperability reports available  Y

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