VF360 3U OpenVPX Conduction-cooled FPGA & DSP Processing module
Board Image
Block Diagram
Overview
The VF360 is a 3U OpenVPX module that leverages on Intel® Stratix® V FPGA andTexas Instruments KeyStone Multicore DSP technology to provide an ultra-highbandwidth processing platform, ideally suited for computation and bandwidthintensive applications such as Radar, Networking, SIGINT, EW, SDR and Video.The onboard multicore DSP from Texas Instruments provides the flexibility toperform complex post processing functions more suited for the processordomain. High bandwidth communication between the DSP and FPGA is providedthrough both PCIe and Serial Rapid IO (SRIO) interfaces.The Stratix� V FPGA has two banks of dedicated DDR3 and QDRII+ memories foralgorithms with high bandwidth and/or large memory size requirements. Highspeedserial interfaces to the OpenVPX data plane and the FMC site creates abundant FPGA IO throughput.The VF360 acts as an FMC carrier to provide a modular solution that accommodatesa wide range of I/O requirements.The VF360 conforms to the OpenVPX standard and operates as a Payloadmodule with System Controller capability. Both air-cooled and conduction cooledversions are available. Further flexibility is provided through build options to cater for10 different FPGAs from Intel Stratix V GX and GS device families
Development Kit Software Contents
- VF360 Board Support Package with Linux distribution (drivers), Sample application and Firmware Reference Design
Support Document
File Name | Description | Version |
---|---|---|
doc-us-dsnbk-48-0904142401-vf360-um.pdf | VF360 User Manual | 04 |
Board Quality Metrics
Basic |
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Latest version of Quartus supported | 14.1 |
Required Collateral Available | |
User Guide | Y |
Board Schematics | N |
Reliability / Quality Assurance | |
Defects per Million Opportunities (DPMO) | 1 |
Parts per Million (PPM) | 10000 |
Board Policy | |
Return Material Authorization (RMA) Policy | 12 Months warranty |
Compliance | |
RoHS Compliant | Y |
CE Compliant | N. CE testing not yet completed |
Conflict Mineral Policy Compliant |
N |
Test Plan Summary | |
The Sample application tests all main functions, DDR & QDR memories, PCIe, SRIO & SERDES links \n \nFM500 companion FMC module with USB debug interfaces for FPGA and DSP (optional) \n \nVR300 companion Rear Transition module with USB debug interfaces for FPGA and DSP plus Ethernet (optional) \n \n3-slot OpenVPX Development Rack with power supply and fan (optional) |
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Additional Compliance | |
ISO 9000 & 9001 |
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