100G MAC + PCS (100GBASE-R4/R10)
Block Diagram
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Supported Device Family:
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Overview
The 100G Ethernet MAC and PCS is the industry leading solution for latency critical Ethernet applications such as data center Ethernet switches. The core is designed using advanced techniques leading to unmatched, ultra-low gate count utilization and amazing latency performances.The IP core supports full wire line speed with a 64-byte packet length. It also supports back-to-back or mixed length traffic, up to jumbo frame size, with no dropped packets.
Features
- Compliant with the IEEE 802.3-2012 High Speed Ethernet Standard
- Highly optimized implementation resulting in ultra-low latency and very low gate count
- Soft PCS logic (100GBASE-R4/R10) interfacing to four (4) serial transceivers at 25.78125Gbps or 10 transceivers at 10.3125Gbps
- Programmable Tx and Rx path VLAN detection
- Configurable statistics vector and collector on transmit and receive MAC/PCS data
Device Utilization and Performance
Getting Started
Complete Intel Arria® 10 reference design which will be including:- 100G MAC & PCS IP integrated with high-speed transceivers, clock and CPU interface- Software Command Line Interface (CLI) to configure and monitor statistics- Simple RTL test benches (optional Verification IP - UVM based)- Product documentation, register mapping
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2016 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | N |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | Optional Verification IP |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | Y |
| Driver OS support | Linux |
| Implementation | |
| User Interface | Other: Custom data bus |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Mentor Graphics (Modelsim, Questa) |
| Hardware validated | N. Altera Board Name HiTech Global: HTG-S5-PCIE-A7 |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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