From Northwest Logic

Expresso DMA Bridge Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless

Evaluation Method: OpenCore

Technology: Basic Functions: DMA

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V

Segments:

Supported Device Family:

Solution Type:

Overview

The Northwest Logic Expresso DMA Bridge core provides high performance DMA and/or bridging between PCIe and AXI for both endpoint and rootport applications. Using the core eliminates the need for the user to implement their own DMA design significantly reducing development time and risk. In addition, Northwest Logic provides companion Windows and Linux Expresso DMA drivers. The Expresso DMA Driver works hand-in-hand with the Expresso DMA Bridge core. Contact Northwest Logic for more information. Northwest Logic also provides IP core customization services.

Features

Provides complete rootport bridging support
Provides high-performance, scatter-gather DMA operation
Supports memory-mapped/streaming (FIFO) DMA operation
Can be configured with multiple DMA Channels which are independently controlled by software
Works with Northwest Logic soft Expresso cores and FPGA hard cores

Device Utilization and Performance

Contact Northwest Logic

Getting Started

Includes Core (netlist or source code), Comprehensive testbench (Source code), Complete documentation and Expert technical support and maintenance updates. For additional information, contact Northwest Logic, Inc. at: Northwest Logic, Inc. 1100 NW Compton Drive, Ste. 100 Beaverton, OR 97006 Tel: (503) 533-5800 x308 Fax: (503) 533-5900 Email: info@nwlogic.com Website: www.nwlogic.com

IP Quality Metrics

Basic
Year IP was first released	2014
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP	Expert technical support
Parameterization GUI allowing end user to configure IP	N
IP core is enabled for OpenCore Plus Support	N
Source language	Verilog
Testbench language	Verilog
Software drivers provided	Y
Driver OS support	Windows and Linux
Implementation
User Interface	AXI; Other: Avalon-ST
IP-XACT Metadata included	N
Verification
Simulators supported	Aldec, Cadence, Mentor Graphics ModelSim PE/DE/SE and Questa, Synopsys VCS
Hardware validated	Y. Altera Board Name : Various - See Intel Core Size and Speed document from Northwest Logic
Industry standard compliance testing performed	N
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.

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