Expresso DMA Bridge Core
Block Diagram

Overview
The Northwest Logic Expresso DMA Bridge core provides high performance DMA and/or bridging between PCIe and AXI for both endpoint and rootport applications. Using the core eliminates the need for the user to implement their own DMA design significantly reducing development time and risk. In addition, Northwest Logic provides companion Windows and Linux Expresso DMA drivers. The Expresso DMA Driver works hand-in-hand with the Expresso DMA Bridge core. Contact Northwest Logic for more information. Northwest Logic also provides IP core customization services.
Features
- Provides complete rootport bridging support
- Provides high-performance, scatter-gather DMA operation
- Supports memory-mapped/streaming (FIFO) DMA operation
- Can be configured with multiple DMA Channels which are independently controlled by software
- Works with Northwest Logic soft Expresso cores and FPGA hard cores
Getting Started
Includes Core (netlist or source code), Comprehensive testbench (Source code), Complete documentation and Expert technical support and maintenance updates. For additional information, contact Northwest Logic, Inc. at: Northwest Logic, Inc. 1100 NW Compton Drive, Ste. 100 Beaverton, OR 97006 Tel: (503) 533-5800 x308 Fax: (503) 533-5900 Email: info@nwlogic.com Website: www.nwlogic.com
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2014 |
Latest version of Quartus supported | 15.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | Expert technical support |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | N |
Source language | Verilog |
Testbench language | Verilog |
Software drivers provided | Y |
Driver OS support | Windows and Linux |
Implementation | |
User Interface | AXI; Other: Avalon-ST |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | Aldec, Cadence, Mentor Graphics ModelSim PE/DE/SE and Questa, Synopsys VCS |
Hardware validated | Y. Altera Board Name : Various - See Intel Core Size and Speed document from Northwest Logic |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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