From Northwest Logic

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Documentation

DSI-2 (MIPI) Controller Core

Overview

Features

Device Utilization

Getting Started

IP Quality Metrics

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Wireless, Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: Serial

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V

Overview

The DSI-2 Controller Core is Northwest Logic’s second generation DSI controller core. It is further optimized for high performance, low power and small size. It is available in 64 and 32 bit core widths. The 64 bit core width can support 1-4 D-PHY data lanes (8 bit PPI) and 1-4 C-PHY lanes (16 bit PPI). The 32 bit core width an support 1-4 D-PHY data lanes (8 bit PPI) and 1-2 C-PHY lanes (16 bit PPI). The core implements all three layers defined by the DSI-2 standard: Pixel to Byte Packing, Low Level Protocol, and Lane Management and is fully compliant with the DSI-2 standard. Separate Host (Tx) and Peripheral (Rx) versions of the core are provided. The core’s native interface provides an easy-to-use data and control/status packet interfaces. The data interfaces provided with optional DPI-2 interface adapter. The core supports command and video modes and all data types. The core is delivered fully integrated and verified with the user’s target D/C-PHY.

Features

  • Fully DSI-2 standard compliant
  • 64 and 32 bit core widths
  • Host (Tx) and Peripheral (Rx) versions
  • 1-4, 2.5+ Gbit/s D-PHY data lane support
  • 1-4, 2.5+ Gsym/s C-PHY lane (trio) support

Device Utilization and Performance

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Getting Started

Includes Core (netlist or source code), Comprehensive testbench (Source code), Complete documentation and Expert technical support and maintenance updates. For additional information, contact Northwest Logic

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
 Y
Any additional customer deliverables provided with IP
Expert technical support
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceOther: Video Interface
IP-XACT Metadata includedN
Verification
Simulators supportedAldec, Cadence, Mentor Graphics ModelSim PE/DE/SE and Questa, Synopsys VCS
Hardware validated Y. Altera Board Name Various - See Altera Core Size and Speed document from Northwest Logic
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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