DSI-2 (MIPI) Controller Core
Block Diagram

Overview
The DSI-2 Controller Core is Northwest Logic’s second generation DSI controller core. It is further optimized for high performance, low power and small size. It is available in 64 and 32 bit core widths. The 64 bit core width can support 1-4 D-PHY data lanes (8 bit PPI) and 1-4 C-PHY lanes (16 bit PPI). The 32 bit core width an support 1-4 D-PHY data lanes (8 bit PPI) and 1-2 C-PHY lanes (16 bit PPI). The core implements all three layers defined by the DSI-2 standard: Pixel to Byte Packing, Low Level Protocol, and Lane Management and is fully compliant with the DSI-2 standard. Separate Host (Tx) and Peripheral (Rx) versions of the core are provided. The core’s native interface provides an easy-to-use data and control/status packet interfaces. The data interfaces provided with optional DPI-2 interface adapter. The core supports command and video modes and all data types. The core is delivered fully integrated and verified with the user’s target D/C-PHY.
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2016 |
Latest version of Quartus supported | 17.0 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | Expert technical support |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | N |
Source language | Verilog |
Testbench language | Verilog |
Software drivers provided | N |
Driver OS support | N/A |
Implementation | |
User Interface | Other: Video Interface |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | Aldec, Cadence, Mentor Graphics ModelSim PE/DE/SE and Questa, Synopsys VCS |
Hardware validated | Y. Altera Board Name Various - See Altera Core Size and Speed document from Northwest Logic |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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