DSI (MIPI) Controller Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless

Evaluation Method: OpenCore

Technology: Interface Protocols: Serial

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V


Northwest Logic's DSI Controller Core is part of Northwest Logic's MIPI Solution. This solution is designed to achieve maximum MIPI throughput while being easy to use. The core implements all three layers defined by the DSI Specification: Pixel to Byte Packing, Low Level Protocol, and Lane Management, and is fully compliant with the DSI specification. Separate Host (TX) and Peripheral (RX) versions of the core are provided. The core provides 4 data and 1 control/status packet interfaces. The data interfaces can be optional adapters to DBI-B/C and DPI interfaces. The control/status interface can be optionally adapted to an AXI interface. The core supports command and video modes, 1-4 data lanes at 1.5+ Gbps and all data types. The core uses the byte lane clock, minimizing power consumption and ensuring the core can be used in older process technologies. The core is delivered fully integrated and verified with the user's target MIPI PHY. Contact Northwest Logic for more information.


  • Host (Tx) and Peripheral (Rx) versions available
  • 1-4 data lane support
  • Fully DSI Specification Compliant
  • High-performance and easy to-use core

Device Utilization and Performance

Contact Northwest Logic

Getting Started

Includes Core (netlist or source code), Comprehensive testbench (Source code), Complete documentation and Expert technical support and maintenance updates. For additional information, contact Northwest Logic, Inc. at: Northwest Logic, Inc. 1100 NW Compton Drive, Ste. 100 Beaverton, OR 97006 Tel: (503) 533-5800 x308 Fax: (503) 533-5900 Email: info@nwlogic.com Website: www.nwlogic.com

IP Quality Metrics

Year IP was first released2011
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Expert technical support
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Testbench languageVerilog
Software drivers providedN
Driver OS supportN/A
User InterfaceOther: DBI, DPI, Packet
IP-XACT Metadata includedN
Simulators supportedAldec, Cadence, Mentor Graphics ModelSim PE/DE/SE and Questa, Synopsys VCS
Hardware validated Y. Altera Board Name : Various - See Altera Core Size and Speed document from Northwest Logic
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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