From Northwest Logic

CSI-2 (MIPI) Controller Core V2

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless

Evaluation Method: OpenCore

Technology: Interface Protocols: Serial

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V

Overview

The CSI-2 Controller Core V2 is Northwest Logic’s second generation CSI-2 controller core. It is further optimized for high performance, low power and small size. It is available in 64 and 32 bit core widths. The 64 bit core width can support 1-8 D-PHY data lanes (8 bit PPI) and 1-4 CPHY lanes (16 bit PPI). The 32 bit core width can support 1-4 D-PHY data lanes (8 bit PPI) and 1-2 C-PHY lanes (16 bit PPI). The core implements all three layers defined by the CSI-2 standard: Pixel to Byte Packing, Low Level Protocol, and Lane Management and is fully compliant with the CSI-2 standard. Separate Transmit (Tx) and Receive (Rx) versions of the core are available. The core’s Local Interface is an easy to use pixel based interface (single, double, quad, octal pixel wide). An optional Hsync/Vsync Video Interface wrapper is also available. The core is delivered fully integrated and verified with the user’s target D/C-PHY. Contact Northwest Logic for a complete list of supported PHYs.

Features

Transmit and receive versions available
1-8, 2.5+ Gbit/s D-PHY data lane support, 1-4, 2.5+ Gsym/s C-PHY lane (trio) support
Fully CSI-2 Specification compliant
Supports all data types
64 and 32 bit core widths

Device Utilization and Performance

Contact Northwest Logic

Getting Started

Includes Core (netlist or source code), Comprehensive testbench (Source code), Complete documentation and Expert technical support and maintenance updates. For additional information, contact Northwest Logic, Inc. at: Northwest Logic, Inc. 1100 NW Compton Drive, Ste. 100 Beaverton, OR 97006 Tel: (503) 533-5800 x308 Fax: (503) 533-5900 Email: info@nwlogic.com Website: www.nwlogic.com

IP Quality Metrics

Basic
Year IP was first released	2016
Latest version of Quartus supported	17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP	Expert technical support
Parameterization GUI allowing end user to configure IP	N
IP core is enabled for OpenCore Plus Support	N
Source language	Verilog
Testbench language	Verilog
Software drivers provided	N
Driver OS support	N/A
Implementation
User Interface	Other: Pixel, Video, Packet
IP-XACT Metadata included	N
Verification
Simulators supported	Aldec, Cadence, Mentor Graphics ModelSim PE/DE/SE and Questa, Synopsys VCS
Hardware validated	Y. Altera Board Name : Various - See Altera Core Size and Speed document from Northwest Logic
Industry standard compliance testing performed	N
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.

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