CSI-2 (MIPI) Controller Core V2
Block Diagram

Overview
The CSI-2 Controller Core V2 is Northwest Logic’s second generation CSI-2 controller core. It is further optimized for high performance, low power and small size. It is available in 64 and 32 bit core widths. The 64 bit core width can support 1-8 D-PHY data lanes (8 bit PPI) and 1-4 CPHY lanes (16 bit PPI). The 32 bit core width can support 1-4 D-PHY data lanes (8 bit PPI) and 1-2 C-PHY lanes (16 bit PPI). The core implements all three layers defined by the CSI-2 standard: Pixel to Byte Packing, Low Level Protocol, and Lane Management and is fully compliant with the CSI-2 standard. Separate Transmit (Tx) and Receive (Rx) versions of the core are available. The core’s Local Interface is an easy to use pixel based interface (single, double, quad, octal pixel wide). An optional Hsync/Vsync Video Interface wrapper is also available. The core is delivered fully integrated and verified with the user’s target D/C-PHY. Contact Northwest Logic for a complete list of supported PHYs.
Getting Started
Includes Core (netlist or source code), Comprehensive testbench (Source code), Complete documentation and Expert technical support and maintenance updates. For additional information, contact Northwest Logic, Inc. at: Northwest Logic, Inc. 1100 NW Compton Drive, Ste. 100 Beaverton, OR 97006 Tel: (503) 533-5800 x308 Fax: (503) 533-5900 Email: info@nwlogic.com Website: www.nwlogic.com
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2016 |
Latest version of Quartus supported | 17.0 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | Expert technical support |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | N |
Source language | Verilog |
Testbench language | Verilog |
Software drivers provided | N |
Driver OS support | N/A |
Implementation | |
User Interface | Other: Pixel, Video, Packet |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | Aldec, Cadence, Mentor Graphics ModelSim PE/DE/SE and Questa, Synopsys VCS |
Hardware validated | Y. Altera Board Name : Various - See Altera Core Size and Speed document from Northwest Logic |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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