Netcope P4

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Test & Measurement, Wireless, Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: Ethernet

Arria Series: Intel® Arria® 10

Stratix Series: Intel® Stratix® 10

Overview

Bringing FPGA acceleration at network engineers' fingertips. Netcope P4 generates FPGA firmware based on P4 language description through a user-friendly web interface. The user does not need to know HDL to program FPGA-based networking devices such as Programmable Accelerator Cards. Get to 100 Gbps packet processing easily with Netcope P4.

Features

  • User-defined packet processing
  • Programmable protocol stack
  • No knowledge of HDL required
  • No synthesis tools or servers needed
  • User-friendly online portal

Device Utilization and Performance

Netcope P4 generates firmware based on user description in P4 language. As such the device utilization fully depends on user code. Contact sales@netcope.com for more details. Target throughput is 100 Gbps at 64B packets. Multiple pipelines can be used to multiply the throughput.

Getting Started

Ask sales@netcope.com for evaluation of the Netcope P4 cloud service.

IP Quality Metrics

Basic
Year IP was first released2017
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
N
Any additional customer deliverables provided with IP
Software drivers and libraries
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportN
Source language
VHDL
Testbench languageVHDL
Software drivers providedY
Driver OS supportCentOS/Ubuntu
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim
Hardware validated Y. Altera Board Name MAP 80/100
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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