Netcope P4
Block Diagram
Overview
Bringing FPGA acceleration at network engineers' fingertips. Netcope P4 generates FPGA firmware based on P4 language description through a user-friendly web interface. The user does not need to know HDL to program FPGA-based networking devices such as Programmable Accelerator Cards. Get to 100 Gbps packet processing easily with Netcope P4.
Device Utilization and Performance
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2017 |
| Latest version of Quartus supported | 18.0 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | N |
| Deliverables | |
Customer deliverables include the following:
|
N |
| Any additional customer deliverables provided with IP | Software drivers and libraries |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | VHDL |
| Testbench language | VHDL |
| Software drivers provided | Y |
| Driver OS support | CentOS/Ubuntu |
| Implementation | |
| User Interface | AXI; Avalon-MM |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim |
| Hardware validated | Y. Altera Board Name MAP 80/100 |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | N |
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