Axonerve Search Engine (Ternary and Exact match engine)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Computer & Storage, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Basic Functions

Arria Series: Intel® Arria® 10

Stratix Series: Intel® Stratix® 10

Overview

Axonerve = axon + nerve Axonerve is an algorithmic table search engine IP core with wildcard search function. Targeting for FPGA-based applications such as Networking (Telecom Carrier, Data Center) and High Performance Computing.

Features

  • ‣Low Latency, ‣High Throughput, ‣Huge Entries, ‣Wildcard Search

Device Utilization and Performance

Model A01 (on-chip model) Throughput 166Msps @166MHz Latency 108ns (18cycle) Key : ~512bit Entry # : 32K~512K Model H01 (HBM model) Throughput 150Msps(Ave.) @166MHz Latency 550-950ns (90-160cycle) Key + Value : ~512bit Entry # : 1M~64M

Getting Started

Deliverable's For Simulation : Encrypted RTL for ModelSim & sample test bench For FPGA implementation : 2-hour time-bombed, encrypted RTL or pre-compiled netlist for target FPGA

IP Quality Metrics

Basic
Year IP was first released2018
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerN
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
Axonerve trial model for evaluation purpose
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportNone
Implementation
User InterfaceAXI
IP-XACT Metadata includedN
Verification
Simulators supportedModel Sim
Hardware validated Y. Altera Board Name Arria10, PAC, etc.
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Intel® or its affiliates. Intel® and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.