Gen4 PCI Express Hybrid Controller with SRIOV

Block Diagram

Solution Type: IP Core

End Market: Automotive, Computer & Storage, Consumer, Industrial, Medical, Test & Measurement, Wireless, Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: PCI Express

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Stratix Series: Stratix® V


Supported Device Family: 

Solution Type: 


MOBIVEIL's PCI Express Hybrid (RC and EP) Controller is ahighly flexible and configurable design targeted for implementations in desktop, server, mobile, networking andtelecom applications. The controller architecture is carefullytailored to optimize link utilization, latency, reliability, powerconsumption, and silicon footprint.


    Device Utilization and Performance

    Maximum Link Width (x1, x2 x4, x8, x16)Maximum TLP data payload size supported (128B to 4KB)Data Path Widths (32, 64, 128, 256bit)8-bit, 16-bit, 32-bit and 64-bit PIPE interface

    Getting Started

    IP Quality Metrics

    Year IP was first released2006
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportwindoes, linux
    User InterfaceAXI; Other: packet interface
    IP-XACT Metadata includedN
    Simulators supportedVCS, NC, Questa
    Hardware validated Y. Altera Board Name Stratix V Reference Kit
    Industry standard compliance testing performed
    If yes, which test(s)?PCISIG
    If yes, on which Altera device(s)?Stratix V
    If Yes, date performed
    IP has undergone interoperability testing
    Interoperability reports available  Y

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