MOBIVEIL's PCI Express Hybrid (RC and EP) Controller is ahighly flexible and configurable design targeted for implementations in desktop, server, mobile, networking andtelecom applications. The controller architecture is carefullytailored to optimize link utilization, latency, reliability, powerconsumption, and silicon footprint.
Device Utilization and Performance
Maximum Link Width (x1, x2 x4, x8, x16)Maximum TLP data payload size supported (128B to 4KB)Data Path Widths (32, 64, 128, 256bit)8-bit, 16-bit, 32-bit and 64-bit PIPE interface
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
AXI; Other: packet interface
IP-XACT Metadata included
VCS, NC, Questa
Y. Altera Board Name Stratix V Reference Kit
Industry standard compliance testing performed
If yes, which test(s)?
If yes, on which Altera device(s)?
If Yes, date performed
IP has undergone interoperability testing
Interoperability reports available
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