Gen4 PCI Express EndPont Controller with SRIOV
Block Diagram
Overview
Mobiveil's PCI Express Endpoint Controller is a highly flexible and configurable design targeted for end-point implementations in desktop, server, mobile, networking and telecom applications. The controller architecture is carefully tailored to optimize link utilization, latency, reliability, power consumption, and silicon footprint
Features
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2005 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | N |
| Driver OS support | Windows, Linux |
| Implementation | |
| User Interface | AXI; Other: packet based |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | VCS, NC, Questa |
| Hardware validated | Y. Altera Board Name Stratix V, Arria 10, Arria10 SoC |
| Industry standard compliance testing performed | Y |
| If yes, which test(s)? | PCISIG |
| If yes, on which Altera device(s)? | Stratix V |
| If Yes, date performed | 01/01/2014 |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | Y |
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