Gen4 PCI Express EndPont Controller with SRIOV

Block Diagram

Solution Type: IP Core

End Market: Automotive, Computer & Storage, Consumer, Test & Measurement, Wireless, Wireline

Evaluation Method: Source Code

Technology: Interface Protocols: PCI Express

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Stratix Series: Stratix® V


Supported Device Family: 

Solution Type: 


Mobiveil's PCI Express Endpoint Controller is a highly flexibleand configurable design targeted for end-point implementationsin desktop, server, mobile, networking and telecom applications.The controller architecture is carefully tailored tooptimize link utilization, latency, reliability, power consumption,and silicon footprint


    Device Utilization and Performance

    Maximum Link Width (x1, x2 x4, x8, x16)Maximum TLP data payload size supported (128B to 4KB)Data Path Widths (32, 64, 128, 256bit)8-bit, 16-bit, 32-bit and 64-bit PIPE interface

    Getting Started

    IP Quality Metrics

    Year IP was first released2005
    Latest version of Quartus supported15.1
    Altera Customer Use
    IP has been successfully implemented in production with at least one customerY

    Customer deliverables include the following:

    • Design file (encrypted source code or post-synthesis netlist)
    • Simulation model for ModelSim Altera edition
    • Timing and/or layout constraints
    • Testbench or design example
    • Documentation with revision control
    • Readme file
    Parameterization GUI allowing end user to configure IPN
    IP core is enabled for OpenCore Plus SupportN
    Source language
    Testbench languageVerilog
    Software drivers providedN
    Driver OS supportWindows, Linux
    User InterfaceAXI; Other: packet based
    IP-XACT Metadata includedN
    Simulators supportedVCS, NC, Questa
    Hardware validated Y. Altera Board Name Stratix V, Arria 10, Arria10 SoC
    Industry standard compliance testing performed
    If yes, which test(s)?PCISIG
    If yes, on which Altera device(s)?Stratix V
    If Yes, date performed
    IP has undergone interoperability testing
    Interoperability reports available  Y

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