IQ-DSI-Tx MIPI DSI Protocol Engine
Block Diagram

Overview
IQ-DSI-Tx is a MIPI DSI protocol engine/transmitter IP core designed to work with PPI-compatible MIPI D-PHY serial interfaces for driving embedded displays.MIPI DSI Transmitter IP core (IQ-DSI-Tx) together with DPHY-Tx IP core provides highspeed serial interface between a host processor and a MIPI DSI-compliant display module.MIPI DSI Transmitter converts a standard parallel video interface into DSI packets transferred to the physical layer (MIPI D-PHY) through the PHY Protocol Interface (PPI) recommended by the MIPI Alliance.
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2016 |
Latest version of Quartus supported | 17.0 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Parameterization GUI allowing end user to configure IP | Y |
IP core is enabled for OpenCore Plus Support | Y |
Source language | VHDL |
Testbench language | VHDL |
Software drivers provided | N |
Driver OS support | N/A |
Implementation | |
User Interface | Avalon-MM; Other: CVI, PPI |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim Intel FPGA Edition |
Hardware validated | Y. Altera Board Name 10M50 Evaluation Kit, Cyclone V |
Industry standard compliance testing performed | N |
If No, is it planned? | Y |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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