IQ-DSI-Tx MIPI DSI Protocol Engine

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Computer & Storage, Industrial, Medical, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Cyclone Series: Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Overview

IQ-DSI-Tx is a MIPI DSI protocol engine/transmitter IP core designed to work with PPI-compatible MIPI D-PHY serial interfaces for driving embedded displays.MIPI DSI Transmitter IP core (IQ-DSI-Tx) together with DPHY-Tx IP core provides highspeed serial interface between a host processor and a MIPI DSI-compliant display module.MIPI DSI Transmitter converts a standard parallel video interface into DSI packets transferred to the physical layer (MIPI D-PHY) through the PHY Protocol Interface (PPI) recommended by the MIPI Alliance.

Features

  • HS mode transmit at 800+ Mbps
  • Clocked video interface at input
  • PHY-Protocol Interface towards (PPI) towards D-PHY
  • DCS command transmission in HS and LP mode (Avalon-MM register mapped), Readback in LP mode only

Device Utilization and Performance

Utilization on Intel® MAX® 10, 4 lanes:LE: 1906REG: 1167M9K: 18IO: N/AUtilization on Cyclone® V/Cyclone V SoC, 2 lanes:ALM: 1692REG: 1662M9K: 20IO: N/A

Getting Started

The core is used with the respective PPI-compatible MIPI D-PHY Core (IQ-DPHY-Tx). Please contact Mikroprojekt for availability and evaluation in your respective platform.

IP Quality Metrics

Basic
Year IP was first released2016
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportN/A
Implementation
User InterfaceAvalon-MM; Other: CVI, PPI
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim Intel FPGA Edition
Hardware validated Y. Altera Board Name 10M50 Evaluation Kit, Cyclone V
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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