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Documentation

IQ-DPHY-Tx MIPI D-Phy Transmitter

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Cyclone Series: Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Overview

IQ-DPHY-Tx is a MIPI D-Phy transmit physical layer IP core for Intel® FPGA devices. It is designed to work with protocol engines utilizing the PPI interface for accessing the MIPI D-PHY Bus. The MIPI D-PHY specification describes a source synchronous, high-speed, low-power physical layer for the connection of camera and display applications to a host processor. MIPI D-PHY interface is the foundation for MIPI CSI2 and DSI higher layer protocols.The IQ-DPHY-Tx IP core allows FPGA users the ability to transmit data according to MIPI DPHY specification. Communication with the DSI or CSI2 protocol layers is done using the PHY Protocol Interface (PPI) recommended by the MIPI Alliance.

Features

One clock lane and up to four data lanes
Unidirectional high-speed mode with data rate up to 900Mbps
Bidirectional low-power operation modes with data rate of 10 Mbps
PHY-Protocol Interface (PPI) for connection to DSI and CSI-2 protocol layers

Device Utilization and Performance

Utilization on Intel MAX® 10 (4 lanes):LE: 667REG: 565M9K: 0IO: 20Utilization on Cyclone® V/Cyclone V SoC, 2 lanes:ALM: 206REG: 248M9K: 1IO: 12Performance: Achievable IO speeds match the maximum for the given device.

Getting Started

The core is used in both MIPI DSI and CSI-2 IP solutions in conjuction with the respective protocol engine. Please contact Mikroprojekt for availability and evaluation in your respective platform.

IP Quality Metrics

Basic
Year IP was first released	2016
Latest version of Quartus supported	17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	Y
Source language	VHDL
Testbench language	VHDL
Software drivers provided	N
Driver OS support	N/A
Implementation
User Interface	Other: PPI, MIPI D-PHY
IP-XACT Metadata included	N
Verification
Simulators supported	ModelSim Intel FPGA Edition
Hardware validated	Y. Altera Board Name 10M50 Evaluation Kit, Cyclone V
Industry standard compliance testing performed	N
If No, is it planned?	Y
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

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