Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
MAX Series: Intel® MAX® 10, MAX® V
Stratix Series: Stratix® IV, Stratix® V
The Microtronix I2C Master/Slave/PIO IP Core is a complete I2C solution offering three modes of operation and support for standard I2C bus transmission speeds. The I2C Master/Slave core provide a generic memory-mapped bus interface. Also designed as an Intel® Platform Designer (formerly Qsys) component, it integrates easily into any Platform Designer generated system using an Nios® II Avalon bus.
Device Utilization and Performance
Requires 300 LE's for Avalon Master/Slave and 100 LE's for PIO function.
Reference designs are supplied to demonstrate the use of the IP Core.
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Source code optional
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Y. Altera Board Name Cyclone V SoC, Arria IV GX, Arria V, Stratix IV and Stratix IV GX DE4 Dev Kit
Industry standard compliance testing performed
If yes, which test(s)?
If yes, on which Altera device(s)?
Cyclone V SoC
If Yes, date performed
IP has undergone interoperability testing
Interoperability reports available
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