HyperDrive Multi-Port DDR2 Memory Controller

Block Diagram

Solution Type: IP Core

End Market: Industrial, Medical, Military

Evaluation Method: OpenCore, OpenCore Plus

Technology: Memory Interfaces and Controllers: SDRAM

Stratix Series: Stratix® IV

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The Microtronix HyperDrive Multi-port DDR2 Memory Controller IP Core brings FPGA based hardware DDR2 designs to a whole new level of performance. Built around a new DDR2 state machine memory controller which operates at half the DDR2 clock rate, the design optimizes the performance of both the FPGA fabric and I/O structures enabling 400 MHz DDR2 (800 Mbps) performance in a Stratix® II, III or IV device.The memory controller supports burst memory RD/WR access cycles and handles all memory tasks, including initialization and refresh cycles. The core integrates: a burst DDR2 memory controller core, a port arbitrator and an intelligent look-ahead FIFO controller into one easy-to-use core.The core supports up to ten independently clocked, full-rate streaming-data devices operating from one shared high bandwidth memory system.

Features

  • DQS data capture simplifies timing closure
  • Configurable FIFO size optimizes streaming video applications
  • Configurable memory and local bus data width
  • Round-robin bus arbitration
  • GUI auto generates SDC constraints for TimeQuest

Device Utilization and Performance

DDR2 SDRAM Controller: 600 LE's. Write/Read Port: 200/100 LE's. ECC Encoder/Decoder: 350/450 LE's.

Getting Started

Reference designs are supplied to demonstrate the use of the IP Core.

IP Quality Metrics

Basic
Year IP was first released2007
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
N
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportNone required
Implementation
User InterfaceOther: Native RD/WR
IP-XACT Metadata includedN
Verification
Simulators supportedModelSIM
Hardware validated Y. Altera Board Name Arria GX and Stratix III Dev Kits
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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