HyperDrive Multi-Port DDR2 Memory Controller
Block Diagram
Overview
The Microtronix HyperDrive Multi-port DDR2 Memory Controller IP Core brings FPGA based hardware DDR2 designs to a whole new level of performance. Built around a new DDR2 state machine memory controller which operates at half the DDR2 clock rate, the design optimizes the performance of both the FPGA fabric and I/O structures enabling 400 MHz DDR2 (800 Mbps) performance in a Stratix® II, III or IV device.The memory controller supports burst memory RD/WR access cycles and handles all memory tasks, including initialization and refresh cycles. The core integrates: a burst DDR2 memory controller core, a port arbitrator and an intelligent look-ahead FIFO controller into one easy-to-use core.The core supports up to ten independently clocked, full-rate streaming-data devices operating from one shared high bandwidth memory system.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2007 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
N |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | VHDL |
| Testbench language | VHDL |
| Software drivers provided | N |
| Driver OS support | None required |
| Implementation | |
| User Interface | Other: Native RD/WR |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSIM |
| Hardware validated | Y. Altera Board Name Arria GX and Stratix III Dev Kits |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | N |
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