Camera Link Transceiver IP Core

Block Diagram

Solution Type: IP Core

End Market: Industrial

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Cyclone Series: Cyclone® IV

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The Microtronix Camera Link Transceiver IP Core is designed for building vision systems incorporating Camera Linkâ„¢ communication interfaces including Base, Medium & Full Channel Link configurations. The core supports camera control signals, serial communication, and video data. It is designed for building both Camera and Frame Grabber devices.

Features

  • Supports 8-bit, 10-tap Base, Medium & Full Camera Link interfaces
  • Supports 64-bit and 80-bit extended Full configurations
  • Camera and Frame Grabber configurations
  • 7:1 Camera Link Serializer/Deserializer (SerDes)
  • Auto Link alignment of Medium and Full Camera Link sources

Device Utilization and Performance

The IP supports transmission clock rates to 85 MHz. in Cyclone®, Stratix® & Arria® devices.Resource requirements: CL Full Receiver, 840LE, CL Full Transmitter, 870LE

Getting Started

Intel® Quartus® Prime II Reference Design supporting a Camera Link Base, Medium & Full configurations are supplied. Camera Link Receiver and Camera Link Transmitter HSMC Daughter Cards are available for hardware prototyping.

IP Quality Metrics

Basic
Year IP was first released2011
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
JAVA Configuratin GUI
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
VHDL
Testbench languageVHDL
Software drivers providedN
Driver OS supportNot applicable
Implementation
User InterfaceOther: Camera Link
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim
Hardware validated Y. Altera Board Name Cyclone IV and Arria IV GX Development Kit
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  N

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