Camera Link Transceiver IP Core
Block Diagram
Overview
The Microtronix Camera Link Transceiver IP Core is designed for building vision systems incorporating Camera Linkâ„¢ communication interfaces including Base, Medium & Full Channel Link configurations. The core supports camera control signals, serial communication, and video data. It is designed for building both Camera and Frame Grabber devices.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2011 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | JAVA Configuratin GUI |
| Parameterization GUI allowing end user to configure IP | Y |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | VHDL |
| Testbench language | VHDL |
| Software drivers provided | N |
| Driver OS support | Not applicable |
| Implementation | |
| User Interface | Other: Camera Link |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim |
| Hardware validated | Y. Altera Board Name Cyclone IV and Arria IV GX Development Kit |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | N |
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