End Market: Broadcast, Medical, Military, Test & Measurement
Evaluation Method: OpenCore Plus
Technology:Memory Interfaces and Controllers: SDRAM
Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
Supported Device Family:
The Microtronix Avalon Multi-port SDRAM Memory Controller IP Core is designed for maximizing the performance of an Intel® Nios® II processor in Avalon' multi-master streaming data systems. Advanced design features enable maximum system clock rates using low speed FPGA's and standard memory devices, lowering your production cost, and saving you money.The Avalon-MM slave ports can be independently clocked allowing the system to be partitioned and optimized to achieve maximum performance. Supporting post memory read and write cycles, the data FIFO's effectively double memory bandwidth on sequential address or FIFO cache hits. FIFO depth can be tailored for either streaming or random access.
Intel Quartus® Prime II reference designs are supplied for a number of Intel FPGA development boards.
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Y. Altera Board Name Arria GX and Stratix III Dev Kits
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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