Avalon Multi-port Front End IP Core
Block Diagram

Overview
The Microtronix Avalon Multi-port Front End provides a complete, easy-to-use solution for interfacing multiple Avalon Memory Masters to a single Avalon Memory Mapped Slave such as Intel® FPGA's line of memory controller IP cores.The Avalon MPFE integrates easily into any Intel® Quartus® Prime II Platform Designer (formerly Qsys) project. It is designed to optimize the performance of Avalon bus based video and streaming data systems. It supports one Avalon Memory Mapped Master port and up to 26 Avalon Memory Mapped Slave ports. The MPFE supports independent clocks for each slave and implements buffers in on-chip memory for each port to support high speed data transfer to the master port.
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2016 |
Latest version of Quartus supported | 15.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
N |
Parameterization GUI allowing end user to configure IP | Y |
IP core is enabled for OpenCore Plus Support | Y |
Source language | Verilog |
Testbench language | Verilog |
Software drivers provided | N |
Driver OS support | Not required |
Implementation | |
User Interface | Avalon-MM |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSIM |
Hardware validated | Y. Altera Board Name Altera Cyclone V SOC Board |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | Y |
Interoperability reports available | N |
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