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Documentation

Avalon Multi-port Front End IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: Basic Functions: Bridges and Adaptors

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V

Overview

The Microtronix Avalon Multi-port Front End provides a complete, easy-to-use solution for interfacing multiple Avalon Memory Masters to a single Avalon Memory Mapped Slave such as Intel® FPGA's line of memory controller IP cores.The Avalon MPFE integrates easily into any Intel® Quartus® Prime II Platform Designer (formerly Qsys) project. It is designed to optimize the performance of Avalon bus based video and streaming data systems. It supports one Avalon Memory Mapped Master port and up to 26 Avalon Memory Mapped Slave ports. The MPFE supports independent clocks for each slave and implements buffers in on-chip memory for each port to support high speed data transfer to the master port.

Features

Five priority levels for arbitration of port service requests
Up to 26 Avalon Memory Mapped Slave interfaces
User configurable cache for each Slave port
Each slave port can use an independent clock
Two Avalon Slave port types: Burst Slave and Random Slave

Device Utilization and Performance

Arbitration Controller: 4,000 LEs, Avalon Burst Port: 240 LEs (per port), Avalon Burst Port: 1200 LEs (per port).Typical Avalon-MM bus interconnect clock rate: 175 MHz

Getting Started

Intel Quartus Prime II application example for Intel FPGA development board

IP Quality Metrics

Basic
Year IP was first released	2016
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	N
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	Y
Source language	Verilog
Testbench language	Verilog
Software drivers provided	N
Driver OS support	Not required
Implementation
User Interface	Avalon-MM
IP-XACT Metadata included	N
Verification
Simulators supported	ModelSIM
Hardware validated	Y. Altera Board Name Altera Cyclone V SOC Board
Industry standard compliance testing performed	N
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	Y
Interoperability reports available	N

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