End Market: Broadcast, Consumer, Industrial, Medical, Military, Test & Measurement
Evaluation Method: OpenCore Plus
Technology:Memory Interfaces and Controllers: SDRAM
Cyclone Series: Cyclone® IV
MAX Series: MAX® V
Stratix Series: Stratix® IV
The Microtronix Avalon Mobile DDR SDRAM Memory Controller IP Core is designed for building high-performance Avalon-MM / Avalon-ST multi-master streaming data systems. Advanced design features enable maximum system clock rates using low speed FPGA's and standard memory devices lowering your production cost, and saving you money.
Supports all standard Mobile DDR SDRAM devices
1 to 16 Avalon® independent local bus port interfaces
Device utilization: SDRAM Controller - 700 LE, Avalon Random Port - 500 LE, Avalon Burst Port 500 LEMemory performance: Arria® II GX - 200MHz, Cyclone® IV - 167MHz, Stratix® IV - 200MHz
Reference designs are available for Intel® FPGA development boards.
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Y. Altera Board Name Cyclone III IV, Arria IV GX and Stratic IV GX Development bolards
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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