Mercury Ensemble IOM 300 XMC Streaming IO
Board Image

Block Diagram

Overview
The Ensemble IOM-300 series are rugged, programmable I/O XMC modules and the industry's first fiber-optic modules which are supported by two FPGAs devices. The primary Intel® industrial-grade Stratix® V FPGA is a formidable, customizable processing resource for low-latency signal processing and is supported by a second configuration-FPGA that enables in-mission, real-time image refreshes. Each of the module's twelve channels may be programmed for data distribution with or without customization from the primary FPGA device.The configuration-FPGA, with its own PCIe pipe, hosts Mercury's next-generation protocol offload engine technology (POET), enabling Ensemble IOM-300 modules to receive mission and system-level changes in real-time. POET preserves existing IP with its backward compatibility with software protocols which include Interprocessor Communication System (ICS) and Message Passing Interface/Open Fabrics Enterprise Distribution (MPI/OFED).
Development Kit Software Contents
- OpenFDK FPGA Development Kit
- System Verification Environment (SVE)
- Linux support package / board support package
- OpenCL support
Support Document
File Name | Description | Version |
---|---|---|
doc-us-dsnbk-277-4304292206-3135-00e-0715-ds-ioseries.pdf | overview | 1 |
Board Quality Metrics
Basic |
|
---|---|
Latest version of Quartus supported | 15.1 |
Required Collateral Available | |
User Guide | Y |
Board Schematics | N |
Reliability / Quality Assurance | |
Defects per Million Opportunities (DPMO) | N/A |
Parts per Million (PPM) | N/A |
Board Policy | |
Return Material Authorization (RMA) Policy | A Return Material Authorization Number (RMA#) is required to return any product sold by Mercury Systems (MRCY). An RMA# can be requested by completing the RMA Request on support.mrcy.com |
Compliance | |
RoHS Compliant | N |
CE Compliant | N. Military grade equipment |
Conflict Mineral Policy Compliant |
Y |
Test Plan Summary | |
Simulation and Verification Environment (SVE) that allows complete end-to-end simulation and design verification for Mercury FPGA-based systems. It is designed to enable application developers to quickly model and verify application logic, dramatically reducing time to market. |
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Additional Compliance | |
ISO 9000 & 9001 |
Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.