Sira Accelerator Function Unit

System Diagram

Arria Series: Intel® Arria® 10

Altera: Intellectual Property: Accelerator Function, Compiler Tool; Segment: Artificial Intelligence, Data Analytics, Financial, Networking


Sira AFU implement the accelerator functions in the FPGA and are exposed to the applications as-a-service the Arka Runtime via high level APIs.


  • - Packet Processing Engine : packet classification, UDP packet termination, TCP packet forwarding
  • - Steam Processing Engine : image reformatting and streaming to host
  • - Deep Learning Inference Engine: optimized engine for inline inferencing

Validated for use with

Quartus Prime Pro Version 18.0
Acceleration Stack version 1.0 Production
Xeon + FPGA Platforms supported Intel® Programmable Accelerator Card with Intel® Arria® 10 GX FPGA
Device Family Arria 10
Cloud Deployments Microsoft Azure

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