Sira Accelerator Function Unit

System Diagram

Arria Series: Intel® Arria® 10

Altera: Intellectual Property: Accelerator Function, Compiler Tool; Segment: Artificial Intelligence, Data Analytics, Financial, Networking

Overview

Sira AFU implement the accelerator functions in the FPGA and are exposed to the applications as-a-service the Arka Runtime via high level APIs.

Features

  • - Packet Processing Engine : packet classification, UDP packet termination, TCP packet forwarding
  • - Steam Processing Engine : image reformatting and streaming to host
  • - Deep Learning Inference Engine: optimized engine for inline inferencing

Validated for use with

Basic
Quartus Prime Pro Version 18.0
Acceleration Stack version 1.0 Production
Xeon + FPGA Platforms supported Intel® Programmable Accelerator Card with Intel® Arria® 10 GX FPGA
Device Family Arria 10
Cloud Deployments Microsoft Azure

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Intel® or its affiliates. Intel® and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.