IEEE 802.3 Clause 74 FEC IP Core
Block Diagram
Overview
The Forward Error Correction (FEC) IP core is designed to comply with the Clause 74 (FEC sublayer for 10GBASE-R, 40GBASE-R, and 100GBASE-R PHYs) of the IEEE 802.3-2008/IEEE 802.3ba-2010 specifications. The Cyclic code (2112, 2080) FEC block lies between PCS and PMA sublayers and provides coding gain to increase the link budget and BER performance.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2010 |
| Latest version of Quartus supported | 16.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | See datasheet |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | N |
| Driver OS support | N/A |
| Implementation | |
| User Interface | Other: Direct parallel |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | ModelSim |
| Hardware validated | Y. Altera Board Name Custom Stratix IV board |
| Industry standard compliance testing performed | N |
| If No, is it planned? | N |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | Y |
Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.