End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline
Evaluation Method: Source Code
Technology:DSP: Error Detection and Correction
Stratix Series: Stratix® IV
The Forward Error Correction (FEC) IP core is designed to comply with the Clause 74 (FEC sublayer for 10GBASE-R, 40GBASE-R, and 100GBASE-R PHYs) of the IEEE 802.3-2008/IEEE 802.3ba-2010 specifications. The Cyclic code (2112, 2080) FEC block lies between PCS and PMA sublayers and provides coding gain to increase the link budget and BER performance.
10GBASE-KR PMD for 10Gbps backplane
40GBASE-KR4 PMD for 40Gbps backplane
40GBASE-CR4 and 100GBASE-CR10 PMDs for 40Gbps and 100Gbps copper cable attachment
Device Utilization and Performance
See datasheet for details.
The FEC IP core is provided as two blocks, an encoder and a decoder, as an implementation of the error correction algorithm for a 66-bit interface, i.e. 66-bit in and 66-bit word out.
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
Other: Direct parallel
IP-XACT Metadata included
Y. Altera Board Name Custom Stratix IV board
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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