GiGE / Triple-speed Ethernet MAC 8-bit core with GMII/RGMII/SGMII interface @ 125MHz/12.5MHz/1.25MHz Solution
Block Diagram

Features
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2010 |
Latest version of Quartus supported | 16.1 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Any additional customer deliverables provided with IP | See datasheet |
Parameterization GUI allowing end user to configure IP | N |
IP core is enabled for OpenCore Plus Support | Y |
Source language | Verilog |
Testbench language | Verilog |
Software drivers provided | Y |
Driver OS support | Linux |
Implementation | |
User Interface | AXI; Avalon-MM |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim |
Hardware validated | Y. Altera Board Name Custom Arria 10 and Stratix V boards |
Industry standard compliance testing performed | N |
If No, is it planned? | N |
Interoperability | |
IP has undergone interoperability testing | Y |
Interoperability reports available | Y |
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