100Gb/s Gigabit Ethernet IP Solution

Block Diagram

Solution Type: IP Core

End Market: Broadcast, Computer & Storage, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Ethernet

Arria Series: Intel® Arria® 10

Stratix Series: Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The 100 Gbps Ethernet IP solution offers a fully integrated IEEE802.3-2015 compliant package for NIC (Network Interface Card) and Ethernet switching applications. A complete reference design using a synthesizable L2 (MAC level) packet generator/checker is also included to facilitate quick integration of the Ethernet IP in a user design. A GUI application interacts with the reference design’s hardware elements through a UART interface (PCIe option is also available). A basic Linux PCIe driver/API is also provided for memory mapped read/write access to the internal registers. 100Gbps Ethernet IP supports advanced features like per-priority pause frames (compliant with 802.3bd specifications) to enable Converged Enhanced Ethernet (CEE) applications like data center bridging that employ IEEE 802.1Qbb Priority Flow Control (PFC) to pause traffic based on the priority levels. NO yearly maintenance fees for upgrades and bug fixes

Features

  • 100Gbps MAC core with AXI-4 Streaming or Avalon Streaming user interface
  • 100Gbps (100GBase-R) PCS core with support for CAUI-4 (-C4 option) and CAUI-10 (-C10 option) interfaces
  • Technology dependent transceiver wrapper for Altera FPGAs
  • Statistics counter block (for RMON and MIB)
  • MDIO and I2C cores for optical module status and control

Device Utilization and Performance

Utilization and performance depends on the devices and options selected. See DataSheets at http://mantaro.com/products/fpga-ip-cores.htm for details.

Getting Started

A complete reference design using a synthesizable L2 (MAC level) packet generator/checker is also included to facilitate quick integration of the Ethernet IP in a user design. A GUI application interacts with the reference design’s hardware elements through a UART interface (PCIe option is also available). A basic Linux PCIe driver/API is also provided for memory mapped read/write access to the internal registers.

IP Quality Metrics

Basic
Year IP was first released2009
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
See datasheet for details
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedY
Driver OS supportLinux
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim
Hardware validated Y. Altera Board Name Custom Arria 10 and Stratix V boards
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
Y
Interoperability reports available  Y

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