MECHATROLINK-III Master/Slave IP

Block Diagram

Solution Type: IP Core

End Market: Industrial

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Ethernet

Cyclone Series: Cyclone® V, Cyclone® V SoC

Overview

MECHATROLINK-III Master/Slave IP together with CPU communicates with the products adapting MECHATROLINK-III standardized by MECHATROLINK Members Association.

Features

  • Functionally compatible with JL-100 which is the ASIC for MECHATROLINK-III Master/Slave communication.
  • Parameters required for MECHATROLINK-III communication are set either by cpu or through external pins.
  • Certified by MECHATROLINK Members Association.

Device Utilization and Performance

Cyclone® V, Logic(ALMs)=8.5k; Registers=16095; RAM Blocks=62.Note: This device utilization doesn't include sample interfaces and other circuits.

Getting Started

Customers can request and get the Evaluation License for 1 month period as default for free.For your evaluation, you can refer to the demo configuration of the IP at https://www.m-pression.com/solutions/hardware/mechatrolink-iiiConfiguring the target device of the IP for your evaluation, the boards below are suggested to use.- "Sodia board" available at https://www.mouser.com/ProductDetail/Mpression/ALTSODIAC5ST/?qs=5aG0NVq1C4x8aOMnmWA6Tg==- Systec SY-M3-03 from SystecFor further information, please contact Macnica sales office by email to AtdSpl@macnica.co.jp or Inquiry Form at https://www.m-pression.com/contact/inquiry

IP Quality Metrics

Basic
Year IP was first released2017
Latest version of Quartus supported16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportNone
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim/QuestaSim
Hardware validated Y. Altera Board Name Mpression SODIA Board
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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