From Macnica, Inc.

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Documentation

ION 8b/10b High Speed Serial Interface IP

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Medical

Evaluation Method: OpenCore Plus

Technology: Interface Protocols

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® V, Cyclone® V SoC

Overview

ION 8b10b is a high-speed serial interface targeting applications with inter-chip and inter-board connections. Lightweight link layer protocol provides one-to-one data movement via one or more high-speed serial lanes.

Features

8-Gbps maximum transmission rate per lane (however, depends on the FPGA used)
Supports up to 16 lanes
Supports CRC function
Supports Scrambler function
Supports asymmetrical link

Device Utilization and Performance

In case 2Lane,Full-Duplex, CRC Enabled, and Cyclone® V GX 3.125Gbps configuration : 3.4kALM,4.3kRegs

Getting Started

Customers can request and get the Evaluation License for 1 month period as default for free.In order to prepare your evaluation without waste, such as preparation of boards or kits, please contact Macnica sales office by email to AtdSpl@macnica.co.jp or Inquiry Form at https://www.m-pression.com/contact/inquiryAnother site you can refer to: https://www.m-pression.com/solutions/hardware/ion-8b10b

IP Quality Metrics

Basic
Year IP was first released	2016
Latest version of Quartus supported	16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Parameterization GUI allowing end user to configure IP	N
IP core is enabled for OpenCore Plus Support	Y
Source language	Verilog
Testbench language	Verilog
Software drivers provided	N
Driver OS support	No
Implementation
User Interface	Other: Avalon-ST
IP-XACT Metadata included	N
Verification
Simulators supported	ModelSim/QuestaSim
Hardware validated	Y. Altera Board Name Nitro/Arria 10 GX Devkit/Arria V GX Starterkit
Industry standard compliance testing performed	N
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

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