CoaXPress 1.1 Device IP

Block Diagram

Solution Type: IP Core

End Market: Industrial, Military

Evaluation Method: OpenCore Plus

Technology: Interface Protocols

Arria Series: Intel® Arria® 10; Intel® Arria® 10 SoC

Cyclone Series: Intel® Cyclone® 10: Intel® Cyclone® 10 GX


CoaXPress is defined by JIIA (Japan Industrial Imaging Association) for high speed image data transmission and intended mainly for Machine Vision applications. CoaXPress uses 75Ω coaxial cable as a physical medium and supports transfer rate up to 6.25Gbps/cable.Utilizing this IP and reference design involved makes you easily accomplish a device compliant with CoaXPress.Macnica has got much experience about GenICam through GigE Vision IP and USB3 Vision IP. CoaXPress IP package also includes software library to help you support GenICam.


  • Compliant with CoaXPress Version 1.1.1
  • Data rate up to 6.25Gbps/lane
  • Supports up to 4 Connections
  • Supports up to 4 Streams
  • Supports GenICam

Device Utilization and Performance

Logic=16kALM,Registers=24kBlock RAM=67 M20Ks under the condition that maximum number of connections is 4,maximum number of stream is 4, maximum stream packet size is 4096 bytes and maximum control packet size is 1024 bytes.Note: this resource utilization doesn't include transceiver, Nios® and its work ram, etc.

Getting Started

Customers can request and get the Evaluation License for 1 month period as default for free.In order to prepare your evaluation without waste, such as preparation of boards or kits, please contact Macnica sales office by email to or Inquiry Form at has tested the IP about compatibility with the following frame grabber boards.- BitFlow Cyton-CXP (CYT-PC2-CXP4)- AVAL DATA APX-3664- Euresys Coaxlink Quad G3You can see the demo configuration of the IP at

IP Quality Metrics

Year IP was first released2018
Latest version of Quartus supported17.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVerilog
Software drivers providedY
Driver OS supportBare Metal
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedModelSim/QuestaSim
Hardware validated Y. Altera Board Name Intel Arria 10 GX Development Kit
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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