HEVC/H.265 4kP60 422 12 Bit Video Decoder
Block Diagram
Overview
Korusys are the lead development team of the Intel® FPGA HEVC SoC CODEC's addressing the move from H.264 to HEVC compression. As a result of this engagement Korusys is pleased to offer to the market place the world's first Professional level 12 bit 4kP60 HEVC decoder core for FPGA fabric.Targeted at Broadcast and Contribution markets the IP is already market proven in the leading Video Conferencing solution currently in operation. The core is available with with smallest resource footprint, lowest latency, earliest market availability and proven robustness and error concealment.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2016 |
| Latest version of Quartus supported | 15.1 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | N |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | Y |
| Driver OS support | Linux |
| Implementation | |
| User Interface | Other: Avalon Streaming |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Questasim |
| Hardware validated | Y. Altera Board Name Nallatech 385a |
| Industry standard compliance testing performed | Y |
| If yes, which test(s)? | H.265 Conformance Streams |
| If yes, on which Altera device(s)? | Arria 10 |
| If Yes, date performed | 08/01/2016 |
| Interoperability | |
| IP has undergone interoperability testing | Y |
| Interoperability reports available | N |
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