Korusys are the lead development team of the Intel® FPGA HEVC SoC CODEC's addressing the move from H.264 to HEVC compression. As a result of this engagement Korusys is pleased to offer to the market place the world's first Professional level 12 bit 4kP60 HEVC decoder core for FPGA fabric.Targeted at Broadcast and Contribution markets the IP is already market proven in the leading Video Conferencing solution currently in operation. The core is available with with smallest resource footprint, lowest latency, earliest market availability and proven robustness and error concealment.
4kP60 @ 100 Mbps
420 / 422
8/10/12 bit support
Available as IP core or as an accelerator card
Device Utilization and Performance
90K ALMS for the highest performing variant of the IP core.
Please contact Korusys for detailed documentation for testing the core and the User Guide.
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
Other: Avalon Streaming
IP-XACT Metadata included
Y. Altera Board Name Nallatech 385a
Industry standard compliance testing performed
If yes, which test(s)?
H.265 Conformance Streams
If yes, on which Altera device(s)?
If Yes, date performed
IP has undergone interoperability testing
Interoperability reports available
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