Video Encoder Interface

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V


Video Encoder Interface core accepts unformatted video data (without blanking/synchronization information) in 10-bit Y'CbCr 4:2:2 format and outputs 10-bit synchronized video in conformance with BT.601/656 recommendation to a video encoder.


  • Parallel interface support for 10-bit
  • Programmable polarity of frame clock & line clock
  • YCbCr 4:2:2 data
  • Supports interlace type scan
  • Programmable interface timing (front and back porch)

Device Utilization and Performance

Intel® Cyclone® IV E Logic Element combinational - 727 Logic Element Registers - 429 Embedded Multipliers 9 bit Elements - 9

Getting Started

1. Simple design makes it easier to integrate in many FPGA families 2. Core supports both PAL and NTSC resolution 3. BT656 standard interface

IP Quality Metrics

Year IP was first released2011
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVerilog
Software drivers providedN
Driver OS supportLINUX
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedModelSim DE 10.2
Hardware validated Y. Altera Board Name Any Altera Development kit
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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