SDIO to UART Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

iW-SDIO to UART bridge is a IP core which converts SDIO slave to UART bus interface.

Features

  • Compliant with SD Physical Specification Version 2.00 and SDIO Specification Version 2.00.
  • Supports SPI, 1-bit and 4bit SD modes. & Supports SDIO Interrupt feature.
  • CRC7 checking/generation for Command/Response & Baud generation (DC to 1.5M baud)
  • Supports High Speed Mode (up to 50Mhz) of operation. & Line break generation and detection
  • Data Transfer in Multi Byte and Multi Block mode using CMD53. & Independently controlled transmit, receive, line status, and data set interrupts

Device Utilization and Performance

Intel® Cyclone® IV ELogic Element combinational - 1,902Logic Element Registers - 1,157Memory Bits - 33,024

Getting Started

1. IP can be quickly customized to implement the SDIO to other devices like USB, PHS, Bluetooth and Wi-Fi etc.2. SDIO interface supported by the bridging IP enables a low-cost and small size implementation.

IP Quality Metrics

Basic
Year IP was first released2012
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportLINUX
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim DE 10.2
Hardware validated Y. Altera Board Name iWave's Altera Cyclone V SoC Development Platform
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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