SDIO to UART Controller
Block Diagram

Features
- Compliant with SD Physical Specification Version 2.00 and SDIO Specification Version 2.00.
- Supports SPI, 1-bit and 4bit SD modes. & Supports SDIO Interrupt feature.
- CRC7 checking/generation for Command/Response & Baud generation (DC to 1.5M baud)
- Supports High Speed Mode (up to 50Mhz) of operation. & Line break generation and detection
- Data Transfer in Multi Byte and Multi Block mode using CMD53. & Independently controlled transmit, receive, line status, and data set interrupts
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2012 |
Latest version of Quartus supported | 18.0 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Parameterization GUI allowing end user to configure IP | Y |
IP core is enabled for OpenCore Plus Support | Y |
Source language | Verilog |
Testbench language | Verilog |
Software drivers provided | N |
Driver OS support | LINUX |
Implementation | |
User Interface | Avalon-MM |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim DE 10.2 |
Hardware validated | Y. Altera Board Name iWave's Altera Cyclone V SoC Development Platform |
Industry standard compliance testing performed | N |
If No, is it planned? | Y |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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