SD Memory Slave Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Memory Interfaces and Controllers: Memory Models

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V


The SD Memory Slave controller is designed to reside within SD Memory card. This slave controller provides simple and general-purpose 8-bit interface to user application. This controller handles the SD bus protocol on the card interface side and forwards only the data transfer requests to user logic interface.


  • Compliant with SD Physical Specification Version 3.00 & Supports 1-bit and 4-bit SD Mode
  • Supports Single and Multiple block read and write data transfer & Supports Partial and Misalign Block length option
  • CID Register fields are configurable through header file & CRC16 checking/generation for Data transfer
  • Supports all mandatory SD Command Classes & CRC7 checking/generation for Command/Response
  • Supports Default and High Speed Modes of operation & Supports Standard and High Capacity operations

Device Utilization and Performance

Intel® Cyclone® IV E Logic Element combinational - 1804 Logic Element Registers - 1494 Embedded Multipliers 9 bit Elements -2

Getting Started

1. Helps to emulate the SD card in test card application 2. Core handles SD bus protocol on the card interface and provides simplified interface to user logic 3. Can be used as bridge core between SD memory to custom application 4. Core handle all the housekeeping tasks by itself without user logic intervention 5. Supports both the standard and High capacity operation

IP Quality Metrics

Year IP was first released2011
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVerilog
Software drivers providedN
Driver OS supportLINUX
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedModelSim DE 10.2
Hardware validated Y. Altera Board Name Any Altera Development kit
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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