SATA Host Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Memory Interfaces and Controllers: Memory Interfaces for UniPHY

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V


The SATA Host Core is available for integration into host FPGA designs to provide an industry- compliant SATA 1.5-Gbps, SATA 3.0-Gbps and SATA 6.0 Gbps interface. Serial ATA (SATA) are computer bus standards that have the primary function of transferring data (directly or otherwise) between the FPGA and mass storage devices such as hard disk.


  • Phy layer consists of Transceiver available in the FPGA which convert the parallel data to serial
  • Phy layer supports clock recovery from serial data, 8B/10B encoding and decoding, Byte ordering and word alignment and OOB signalling
  • Link layer supports frame formation by adding the envelope and frame decomposition by removing envelope from received data
  • Transport layer supports 32 bit AXI stream interface for Tx and RX towards user interface
  • Transport layer supports FISes such as Register FIS, DMA Activate FIS, DMA Setup FIS, Data FIS, PIO Setup FIS, Set Device Bits FIS

Device Utilization and Performance

Intel® Cyclone® IV E Logic Element combinational - 2233 Logic Element Registers - 1384 Memory Bits - 150656

Getting Started

1. SATA controller enables interfacing of industry standard Gen 1 or Gen 2 or Gen 3 SSD and SATA disks. 2. Suitable for SATA device which are used as embedded storage system and can be easily interfaced with different processors. 3. Controller provides simple AXI streaming TX and RX interface for the communication with Application layer. 4. Supports Native Command Queuing and most of the primitives and FIS types defined in SATA specification.

IP Quality Metrics

Year IP was first released2014
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVerilog
Software drivers providedN
Driver OS supportLINUX
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedModelSim DE 10.2
Hardware validated Y. Altera Board Name iWave's Altera Cyclone V SoC Development Platform
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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