NAND Flash Controller

Block Diagram

Solution Type: IP Core, Qsys Component

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement

Evaluation Method: OpenCore Plus

Technology: Memory Interfaces and Controllers: Flash

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V


"NAND Flash Memory Controller, 8/16-bit Async Interface, IP not device specific, any device having 8/16 interface can be supported IP capable to do ECC using Hamming Code Support for BBM"


  • Simple streaming interface towards user logic for data read and write
  • Controller supports rich set of NAND commands
  • Core is compliant with Open ONFI standard
  • ECC Logic: Hamming code used to correct 1-bit error and detect 2-bit errors
  • Commands supported from user: Block Erase, Read, Program and Copy-Back Program

Device Utilization and Performance

Intel® Cyclone® IV E Logic Element combinational - 1124 Logic Element Registers - 588 M9K Blocks - 4

Getting Started

This NAND Flash host controller supports 8-bit NAND Flash Interface. It has streaming interface towards user logic for data read and write .The data transfer between the host and NAND flash is carried out using command sequences like Read, Read for Copy Back, Reset, Page Program, Copy-Back Program, Block Erase, Random Data Input, Random Data Output and Read Status. This consists of 2KB data buffer for storing data to be written to NAND Flash and 2KB data buffer for storing read data. NAND Flash Host Controller consists of ECC logic where Hamming code is to correct 1-bit error and detect 2-bit errors. It supports feature of Indentifying factory defined invalid blocks.

IP Quality Metrics

Year IP was first released2011
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog
Software drivers providedY
Driver OS supportLinux
User InterfaceAXI
IP-XACT Metadata includedN
Simulators supportedModelSim
Hardware validated Y. Altera Board Name Any Altera Development kit
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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