ARINC 818-2 IP Core

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Intel® Stratix® 10, Stratix® IV, Stratix® V

Overview

iWave's ARINC IP core is ARINC 818–compliant, which can be implemented on any transceiver based FPGA. It can be used for both transmit-and-receive applications. This core has flexible user interface, allowing for various video parameter configuration. This IP core supports Line Synchronous Mode.

Features

  • Streaming Interface used as Video transmit and receive interface, which provide high throughput video transfer.
  • Pixel Format supported. (Monochrome, RGB, YcbCr, RGBA)
  • Wide range of frames rate supported
  • Line Synchronous Mode supported
  • 32-bit Full Image CRC supported

Device Utilization and Performance

Cyclone® V Logic Elements Combinational:10701 Logic Elements Registers:17671 Memory Bits: 2367944

Getting Started

iWave's ARINC IP core is ARINC 818–compliant. ARINC 818 is a point-to-point, serial protocol for transmission of video, audio and data during blanking period, widely used in AVIONICS ARINC 818 is a low latency protocol uses optical as a transmission medium

IP Quality Metrics

Basic
Year IP was first released2015
Latest version of Quartus supported18.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog; VHDL
Testbench languageVerilog
Software drivers providedY
Driver OS supportLinux
Implementation
User InterfaceOther: Avalon/AXI Streaming inte
IP-XACT Metadata includedN
Verification
Simulators supportedModesim DE, Altera Modelsim
Hardware validated Y. Altera Board Name Altera Stratix IV, CycloneV SoC
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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