From iWave Systems Technologies Pvt. Ltd.

8530 Multi-Protocol Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V

Segments:

Supported Device Family:

Solution Type:

Overview

8530 MPSC Controller (Multi-Protocol Serial Communication Controller) is a general-purpose communication controller which consists of two sets of bi-directional parallel / serial converter circuits for data communication.

Features

Hardware features - Transmit buffer (2 Byte Depth) & Receive buffer (4 Byte Depth) & Interrupt control function
Communication protocol features - Start-stop synchronization & Character oriented protocol (COP) - Mono-sync, Bi-sync, External sync
Encode/decode of NRZ (Non-Return to Zero)
Encode/decode of NRZI (Non-Return to Zero Inverted) & Encode/decode of FM (Frequency Modulation)
Decode in Manchester mode

Device Utilization and Performance

Intel® Cyclone® IV ELogic Element combinational - 5399Logic Element Registers - 1989

Getting Started

1. Controller has facilities for modem controls in both channels2. Controller modem signals are not used then they can be used as general purpose I/O3. Compatible with uPD72001 and 85C304. Controller supports all three serial protocols (UART, Mono-Sync, Bi-Sync, HDLC and SDLC)

IP Quality Metrics

Basic
Year IP was first released	2011
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	Y
Source language	Verilog
Testbench language	Verilog
Software drivers provided	N
Driver OS support	LINUX
Implementation
User Interface	Avalon-MM
IP-XACT Metadata included	N
Verification
Simulators supported	ModelSim DE 10.2
Hardware validated	Y. Altera Board Name Any Altera Development kit
Industry standard compliance testing performed	N
If No, is it planned?	Y
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

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