8530 Multi-Protocol Controller
Block Diagram

Features
- Hardware features - Transmit buffer (2 Byte Depth) & Receive buffer (4 Byte Depth) & Interrupt control function
- Communication protocol features - Start-stop synchronization & Character oriented protocol (COP) - Mono-sync, Bi-sync, External sync
- Encode/decode of NRZ (Non-Return to Zero)
- Encode/decode of NRZI (Non-Return to Zero Inverted) & Encode/decode of FM (Frequency Modulation)
- Decode in Manchester mode
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2011 |
Latest version of Quartus supported | 18.0 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Parameterization GUI allowing end user to configure IP | Y |
IP core is enabled for OpenCore Plus Support | Y |
Source language | Verilog |
Testbench language | Verilog |
Software drivers provided | N |
Driver OS support | LINUX |
Implementation | |
User Interface | Avalon-MM |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim DE 10.2 |
Hardware validated | Y. Altera Board Name Any Altera Development kit |
Industry standard compliance testing performed | N |
If No, is it planned? | Y |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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