8259A Interrupt Controller
Block Diagram

Features
- Eight interrupt request input per chip & Up to 64 interrupt request inputs per system
- Edge or level triggered interrupt request inputs & Individually maskable interrupt requests
- Programmable interrupt request priority orders & Polling operation capability
- Extended mode with cascade connection of external interrupts
- Supports Slave mode in extended mode
Getting Started
1. Can be used to assign priority levels to interrupt outputs 2. Allows cascading of multiple interrupts 2. Compatible with 8259A and uPD71059 3. Two modes of operation make the controller compatible with 8080/85 and 8086/88/286 microprocessors 4. Microcomputer system with I/O devices are serviced with efficient manner by using iW-8259A interrupt controller
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2011 |
Latest version of Quartus supported | 18.0 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Parameterization GUI allowing end user to configure IP | Y |
IP core is enabled for OpenCore Plus Support | Y |
Source language | Verilog |
Testbench language | Verilog |
Software drivers provided | N |
Driver OS support | LINUX |
Implementation | |
User Interface | Avalon-MM |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim DE 10.2 |
Hardware validated | Y. Altera Board Name Any Altera Development kit |
Industry standard compliance testing performed | N |
If No, is it planned? | Y |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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