From iWave Systems Technologies Pvt. Ltd.

8259A Interrupt Controller

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Processors and Peripherals: Peripherals

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Overview

8259A Interrupt Controller is designed to transfer the interrupt with highest priority to the CPU, along with interrupt address information.

Features

Eight interrupt request input per chip & Up to 64 interrupt request inputs per system
Edge or level triggered interrupt request inputs & Individually maskable interrupt requests
Programmable interrupt request priority orders & Polling operation capability
Extended mode with cascade connection of external interrupts
Supports Slave mode in extended mode

Device Utilization and Performance

Intel® Cyclone® IV ELogic Element combinational - 510Logic Element Registers - 163

Getting Started

1. Can be used to assign priority levels to interrupt outputs2. Allows cascading of multiple interrupts2. Compatible with 8259A and uPD710593. Two modes of operation make the controller compatible with 8080/85 and 8086/88/286 microprocessors4. Microcomputer system with I/O devices are serviced with efficient manner by using iW-8259A interrupt controller

IP Quality Metrics

Basic
Year IP was first released	2011
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	Y
Source language	Verilog
Testbench language	Verilog
Software drivers provided	N
Driver OS support	LINUX
Implementation
User Interface	Avalon-MM
IP-XACT Metadata included	N
Verification
Simulators supported	ModelSim DE 10.2
Hardware validated	Y. Altera Board Name Any Altera Development kit
Industry standard compliance testing performed	N
If No, is it planned?	Y
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

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