8251 Serial Controller
Block Diagram

Features
- RS-232-C protocol support & Baud rate generator or timer output selectable as Tx/Rx clock
- Asynchronous communication only & Serial interrupt support & Clock rates of baud rate of x16 or x64
- Character length of 7 or 8 bits & 1 or 2 Stop bits & Break transmission
- Automatic break detection & Full duplex double buffer system & Parity addition/checking
- Error detection for parity, overrun and framing errors
IP Quality Metrics
Basic | |
---|---|
Year IP was first released | 2011 |
Latest version of Quartus supported | 18.0 |
Altera Customer Use | |
IP has been successfully implemented in production with at least one customer | Y |
Deliverables | |
Customer deliverables include the following:
|
Y |
Parameterization GUI allowing end user to configure IP | Y |
IP core is enabled for OpenCore Plus Support | Y |
Source language | Verilog |
Testbench language | Verilog |
Software drivers provided | N |
Driver OS support | LINUX |
Implementation | |
User Interface | Avalon-MM |
IP-XACT Metadata included | N |
Verification | |
Simulators supported | ModelSim DE 10.2 |
Hardware validated | Y. Altera Board Name Any Altera Development kit |
Industry standard compliance testing performed | N |
If No, is it planned? | Y |
Interoperability | |
IP has undergone interoperability testing | N |
Interoperability reports available | N |
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