From iWave Systems Technologies Pvt. Ltd.

80186XL Processor

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Processors and Peripherals: Embedded Processors

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Segments:

Supported Device Family:

Solution Type:

Overview

The 80186XL is a powerful 16-bit microprocessor core, executes instruction list compatible with 80186XL microprocessor. The 80186XL core has a broad set of integrated peripherals, which helps reduce system development time and cost and is compatible with wide range of compilers and debuggers. The design along with multiple peripherals can be fit into single FPGA.

Features

Three programmable independent 16-bit timers & Internal / external input clock selectable
Direct Memory Access Unit & Interrupt Control Unit
Clock Generator & Special fully nested mode support
Thirteen programmable chip-select outputs & Memory or I/O bus cycle decoder
Programmable wait-state generator

Device Utilization and Performance

Intel® Cyclone® IV ELogic Element combinational - 8693 Logic Element Registers - 3189Embedded Multipliers 9 bit Elements - 4

Getting Started

1. Compatible with Intel 80186XL instruction set2. High FPGA integration enables lower BOM cost and smaller board design.3. Supports retarget and merge external peripherals and traditional custom old ASICs.4. Quick migration of 80186XL based designs to an FPGA platform.5. Replacement for 80186XL processor and ASICs.

IP Quality Metrics

Basic
Year IP was first released	2008
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	Y
Source language	Verilog
Testbench language	Verilog
Software drivers provided	N
Driver OS support	LINUX
Implementation
User Interface	Avalon-MM
IP-XACT Metadata included	N
Verification
Simulators supported	ModelSim DE 10.2
Hardware validated	Y. Altera Board Name Any Altera Development kit
Industry standard compliance testing performed	N
If No, is it planned?	Y
Interoperability
IP has undergone interoperability testing	N
Interoperability reports available	N

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