80186EC Processor

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Processors and Peripherals: Embedded Processors

Arria Series: Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The 80186EC is a powerful 16-bit microprocessor core, executes instruction list compatible with 80186EC microprocessor. The 80186EC core has a broad set of integrated peripherals, which helps reduce system development time and cost and is compatible with wide range of compilers and debuggers. The design along with multiple peripherals can be fit into single FPGA

Features

  • Multiplexed 20-bit address and 16-bit data bus & 1M-byte memory space divided into 4 segments
  • Programmable Timer / Counter Unit & Serial Communications Unit
  • Clock Generator & Interrupt Controller Unit
  • Direct Memory Access Unit & Watchdog Timer Unit
  • Multiplexed general purpose Input Output port

Device Utilization and Performance

Intel® Cyclone® IV ELogic Element combinational - 9467 Logic Element Registers - 3599Embedded Multipliers 9 bit Elements -4

Getting Started

1. Compatible with Intel 80186EC instruction set2. High FPGA integration enables lower BOM cost and smaller board design3. Quick migration of 80186EC based designs to an FPGA platform4.Replacement for 80186EC processor and ASICs

IP Quality Metrics

Basic
Year IP was first released2013
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportLINUX
Implementation
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelSim DE 10.2
Hardware validated Y. Altera Board Name Any Altera Development kit
Industry standard compliance testing performed
N
If No, is it planned?Y
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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