TICO Lightweight Encoder (HD/4K/8K)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Wireless, Wireline

Evaluation Method: Source Code

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10

Stratix Series: Stratix® IV, Stratix® V


TICO compression is visually lossless lightweight compression specifically designed for the industry. This revolutionary technology is extremely tiny in FPGAs, fitting the smallest Intel® FPGA devices, robust for real-time operation with no latency.


  • Visually Lossless quality up to 4:1 (even Mathematically lossless at lower bitrate)
  • Fixed latency: down to microseconds Selectable from 1 to x pixel lines
  • 4:2:0; 4:2:2 ; 4;4:4 | 8,10,12 bit | CBR (VBR as option) | RGB , YUV, BAYER
  • Small complexity and ultra-compact codec: easy to implement in low-cost FPGA. Limited internal memory - no external memory require
  • Compatible with different resolutions, from mobile, HD to 4K/8K UHDTV, via multiple usual transport schemes

Device Utilization and Performance

Depends on IP-core configurationFrom HD up to 4K or 8K or more.From Low frame rate to high speedVarious architecture running at various frequencies

Getting Started

Contact intoPIX and Intel PSG for an evaluation and more technical details

IP Quality Metrics

Year IP was first released2014
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
intoPIX HDK framework and reference software
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportN
Source language
Verilog; VHDL
Testbench languageVerilog; VHDL
Software drivers providedN
Driver OS support/
User InterfaceAXI
IP-XACT Metadata includedN
Simulators supportedModelSIM
Hardware validated Y. Altera Board Name Stratix IV, Stratix V, Arria V, Cyclone V, Arria 10
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  Y

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