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Documentation

JPEG2000 Decoder (HD/4K/8K)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Wireless, Wireline

Evaluation Method: Source Code

Technology: DSP: Video and Image Processing

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Overview

intoPIX EMMY® Award-winning JPEG 2000 Encoder and Decoder IP-Cores protect high value images. Handling simultaneously deep color, low and high data rates and extensive JPEG 2000 know-how, intoPIX IP-Cores enable best-in-class picture quality. The IP-Cores are available for the most recent FPGA platforms and ensure lower consumption, lower temperature dissipation and lower bill of material with unprecedented performances. Fully benefiting from a modular architecture (image formats, frame rates and resolutions) and completed with a wide range of companion IP-Cores (video transport, security, memory sharing, ...), the intoPIX solutions provide an easy, timely and cost-effective way to implement JPEG 2000 technology.

Features

JPEG 2000 (ISO/IEC 15444-1) | Compliant with DCI , Broadcast (VSF TR01) , IMF profiles ,...
Classic Latency & Ultra Low Latency modes (<10 milliseconds - unique feature!)
4:2:0; 4:2:2 ; 4;4:4 | 8,10,12,14,16 bit | CBR , VBR | RGB , YUV, RAW BAYER
Fully configurable | Very Low Footprint | High Efficiency and Quality
Visually Lossless quality up to 20:1 | or Math Lossless Mode | Any Bitrate

Device Utilization and Performance

Depends on IP-core configuration From HD up to 4K or 8K or more. From Low frame rate to high speed Various architectures running at various frequencies

Getting Started

Contact intoPIX & Intel PSG for more information or for an evaluation

IP Quality Metrics

Basic
Year IP was first released	2008
Latest version of Quartus supported	15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP	intoPIX HDK framework and reference software
Parameterization GUI allowing end user to configure IP	N
IP core is enabled for OpenCore Plus Support	N
Source language	VHDL
Testbench language	VHDL
Software drivers provided	N
Driver OS support	/
Implementation
User Interface	AXI; Avalon-MM
IP-XACT Metadata included	N
Verification
Simulators supported	/
Hardware validated	Y. Altera Board Name Cyclone V, Arria V, Stratix IV, Stratix V, Arria 10
Industry standard compliance testing performed	N
If No, is it planned?	N
Interoperability
IP has undergone interoperability testing	Y
Interoperability reports available	N

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.

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