SATA 1:1 Speed Bridge with Sandbox (IPP-SA110A-BR)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Intel® Arria® 10, Arria® V

Cyclone Series: Cyclone® V

Stratix Series: Stratix® V


The IntelliProp IPP-SA110A-BR, SATA Bridge with Sandbox IP core provides SATA compliant connections to a SATA host and a SATA device. The host and device connections are speed independent allowing for speed bridging on the SATA connection. Internal visibility to frame contents allows customers to intercept, analyze or manipulate frames on the SATA connection. Applications include: Adding user defined encryption algorithm; the ability to block certain commands from reaching the drive (write blocking); Compression of data/


  • Allows users to intercept data between the SATA Host and Device (Bump in the Wire)
  • Industry proven and compliant SATA interfaces at SATA Gen-1, Gen-2 and Gen-3 speeds
  • Independent speed negotiation on each SATA connection
  • Visibility to all frames allows customers to develop value-added features

Device Utilization and Performance

Please contact IntelliProp for FPGA device specific performance and utilization information.

Getting Started

Please contact IntelliProp at to discuss specific needs for your project.

IP Quality Metrics

Year IP was first released2016
Latest version of Quartus supported16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Simulation script, sample vectors
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportN
Source language
Testbench languageVerilog
Software drivers providedN
Driver OS supportn/a
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Arria V, Arria 10, Stratix V, Cyclone V
Industry standard compliance testing performed
If No, is it planned?N
IP has undergone interoperability testing
Interoperability reports available  N

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