From IntelliProp, Inc.

IntelliProp SATA AHCI Host Core (IPC-SA156A-HI)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Segments:

Supported Device Family:

Solution Type:

Overview

IntelliProp’s IPC-SA156A-HI is an industry standard Serial-ATA (SATA) host interface core that enables customers to use high throughput SATA storage devices. The protocol interface is compliant to the SATA 3.3 specification as defined by the Serial ATA International Organization (SATA-IO). Target applications include Enterprise storage interconnect, High Speed Data Acquisition systems, any system needing to connect ot SATA storage media.

Features

Compliant with the industry standard AHCI specification set by Intel Corporation
Supports auto speed negotiation and single speed locking
Optional: AES-XTS Encryption
Fully Compliant to SATA 1.5, 3.0, and 6.0 industry specifications
Power Modes (partial/slumber) and support for DEVSLP

Device Utilization and Performance

Please contact IntelliProp for FPGA device specific performance and utilization information.

Getting Started

Please contact IntelliProp at info@intelliprop.com to discuss specific needs for your project.

IP Quality Metrics

Basic
Year IP was first released	2014
Latest version of Quartus supported	16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP	RTL Encrypted code; simulation script, vectors & expected results; synthesis or place & route script
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	N
Source language	Verilog
Testbench language	Verilog
Software drivers provided	N
Driver OS support	linux
Implementation
User Interface	AXI; Avalon-MM
IP-XACT Metadata included	N
Verification
Simulators supported	Modelsim
Hardware validated	Y. Altera Board Name Arria II, Arria V, Arria 10, Attila Arria 10, Stratix IV, Stratix V, Cyclone IV, Cyclone V
Industry standard compliance testing performed	Y
If yes, which test(s)?	UNH interoperability
If yes, on which Altera device(s)?	Arria II, Stratix IV
If Yes, date performed	03/05/2010
Interoperability
IP has undergone interoperability testing	Y
Interoperability reports available	Y

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.

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