IntelliProp SATA ADCI Device Core (IPC-SA155A-DT)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V


IntelliProp's SATA ADCI Device interface core that allows companies to build high speed storage devices. The protocol interface is compliant to the SATA 3.3 specification as defined by SATA-IO and is fully verified in pseudo random simulation. Target applications include: internal connections to computer motherboards, E-SATA storage, Hard Disk Drives, or Solid State Drives


  • Application layer (command based) interface with Processor interface (ADCI)
  • Data Interface through FIFOs
  • Processor interface for register access
  • Supports either SerDes, PIPE, or SAPIS interface
  • Synchronous design for easy integration

Device Utilization and Performance

600 Mb/s serial burst, and 550MB/s sustained; Performance is based on the type of drive used in the application. 5549 LUTS, 68368 bit memory (on Arria® II GX). Other FPGAs, like Intel® Arria10 GX, Stratix®V GX will be smaller in size.

Getting Started

Please contact IntelliProp at to discuss specific needs for your project.

IP Quality Metrics

Year IP was first released2014
Latest version of Quartus supported16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
RTL Encrypted code; simulation script, vectors & expected results; synthesis or place & route script
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportN
Source language
Testbench languageVerilog
Software drivers providedN
Driver OS supportlinux
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Arria II, Arria V, Arria 10, Attila Arria 10, Stratix IV, Stratix V, Cyclone IV, Cyclone V
Industry standard compliance testing performed
If yes, which test(s)?UNH interoperability
If yes, on which Altera device(s)?Arria II, Stratix IV
If Yes, date performed
IP has undergone interoperability testing
Interoperability reports available  Y

Design Solutions Network Members provide products and/or services that are sold or licensed by the Member and not Altera or its affiliates. Altera and its affiliates hereby disclaim any express or implied warranty of any kind including warranties of merchantability, noninfringement of intellectual property, or fitness for any particular purpose with respect to any such products and/or services.