From IntelliProp, Inc.

IntelliProp SATA ADCI Device Core (IPC-SA155A-DT)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V

Overview

IntelliProp's SATA ADCI Device interface core that allows companies to build high speed storage devices. The protocol interface is compliant to the SATA 3.3 specification as defined by SATA-IO and is fully verified in pseudo random simulation. Target applications include: internal connections to computer motherboards, E-SATA storage, Hard Disk Drives, or Solid State Drives

Features

Application layer (command based) interface with Processor interface (ADCI)
Data Interface through FIFOs
Processor interface for register access
Supports either SerDes, PIPE, or SAPIS interface
Synchronous design for easy integration

Device Utilization and Performance

600 Mb/s serial burst, and 550MB/s sustained; Performance is based on the type of drive used in the application. 5549 LUTS, 68368 bit memory (on Arria® II GX). Other FPGAs, like Intel® Arria10 GX, Stratix®V GX will be smaller in size.

Getting Started

Please contact IntelliProp at info@intelliprop.com to discuss specific needs for your project.

IP Quality Metrics

Basic
Year IP was first released	2014
Latest version of Quartus supported	16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customer	Y
Deliverables
Customer deliverables include the following: Design file (encrypted source code or post-synthesis netlist) Simulation model for ModelSim Altera edition Timing and/or layout constraints Testbench or design example Documentation with revision control Readme file	Y
Any additional customer deliverables provided with IP	RTL Encrypted code; simulation script, vectors & expected results; synthesis or place & route script
Parameterization GUI allowing end user to configure IP	Y
IP core is enabled for OpenCore Plus Support	N
Source language	Verilog
Testbench language	Verilog
Software drivers provided	N
Driver OS support	linux
Implementation
User Interface	AXI; Avalon-MM
IP-XACT Metadata included	N
Verification
Simulators supported	Modelsim
Hardware validated	Y. Altera Board Name Arria II, Arria V, Arria 10, Attila Arria 10, Stratix IV, Stratix V, Cyclone IV, Cyclone V
Industry standard compliance testing performed	Y
If yes, which test(s)?	UNH interoperability
If yes, on which Altera device(s)?	Arria II, Stratix IV
If Yes, date performed	03/05/2010
Interoperability
IP has undergone interoperability testing	Y
Interoperability reports available	Y

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