IntelliProp SAS Target IP Core (IPC-SS107A-DT)

Block Diagram

Solution Type: IP Core

End Market: Automotive, Broadcast, Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Intel® Arria® 10

Stratix Series: Stratix® IV, Stratix® V

Segments: 

Supported Device Family: 

Solution Type: 

Overview

The IntelliProp IPC-SS107A-DT, SAS Target Core is an industry standard Serial-SCSI (SAS) core that enables device applications to connect to high throughput SAS storage devices. The protocol interface is compliant to the SAS specification as defined by the ANSI T10 Organization and provides an industry compliant SAS 3.0 and 6.0 Gb/s interface. As with all IntelliProp cores, the IPC-SS107A-DT core is fully verified in psuedo-random simulation. Applications include: Internal interconnect for workstation and server storage; External workstations/Enterprise Storage interconnect; HDD /SSD hot-swap environments.

Features

  • Fully compliant to the SAS 3.0 and 6.0 Gb/s industry specifications
  • Processor specific interfaces for register access.
  • Configurable memories for performance and area trade-offs
  • Supports OOB and speed negotiation sequences
  • Auto ACK/NAK transmission, credit management and Open/Close connections

Device Utilization and Performance

Please contact IntelliProp for FPGA device specific performance and utilization information.

Getting Started

Please contact IntelliProp at info@intelliprop.com to discuss specific needs for your project.

IP Quality Metrics

Basic
Year IP was first released2008
Latest version of Quartus supported16.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY
Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Y
Any additional customer deliverables provided with IP
RTL Encrypted code; synthesis or place and route script
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportN
Source language
Verilog
Testbench languageVerilog
Software drivers providedN
Driver OS supportstandalone
Implementation
User InterfaceAXI; Avalon-MM
IP-XACT Metadata includedN
Verification
Simulators supportedModelsim
Hardware validated Y. Altera Board Name Arria V, Arria 10, Stratix IV, Stratix V
Industry standard compliance testing performed
N
If No, is it planned?N
Interoperability
IP has undergone interoperability testing
N
Interoperability reports available  N

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